We already discussed why designers need to do LEC, and we will talk about Conformal LEC flow in this post.

In LEC setup, there are several steps that designers need to follow:

    • Read and elaborate reference design
    • Read and elaborate revised design
    • Specify “notranslate modules” for blackboxing if the module is a macro, or the module has been LECed in block level
    • Set certain constraints, for example, when comparing between RTL and synthesis netlist, set case analysis to ignore scan ports

LEC key point mapping is the next step. In this step, Conformal LEC will first identify primary inputs and outputs, DFF, Latch, Blackboxes, etc. as the key points in both reference design and revised design; then pair corresponding reference and revised key points, and perform LEC comparison after that.

There are 2 LEC mapping method, i.e., name-based and function-based. By default, Conformal LEC will first do name-based mapping, followed by function-based mapping. This approach typically works really well.

In LEC report generation, designers will typically dump the following reports:

    • report unmapped points (-unreachable, -notmapped, -extra)
    • report compare data (-class nonequivalent, -class abort)
    • report black box (check if there’s any unexpected black boxes)
    • report ignored inputs and outputs
    • report pin constraints
    • report output stuck at
    • report floating signals
    • report renaming rule (this guides how LEC performs key point mapping)

LEC non-equivalence debug will be the last step. Debugging typically starts from unmapped points, and possible root cause includes:

    • Not mapped BBOX pins causes NEQs (Use renaming rule if pins names not matched)
    • Not mapped DFF/DLATCH/CUT/PI causes NEQs (Optimize and merge DFF/DLATCH in LEC; Resolve unbalanced loop cutting; Constrain test/scan signals)
    • Incorrect mapping causes NEQs (Remap the incorrectly mapped pairs manually)

After resolving all mapping issues, designers can start debugging real mismatches, and possible root cause includes:

    • Unbalanced floating signals can cause NEQs (Tie off floating pins in RTL, or use “add tie signal” to individually tie each floating Z)
    • Logic optimized differently b/w LEC and implementation causing NEQs
    • Debug phase mapping (Recommended: turn off phase inversion in synthesis; Or auto analysis & remap with phase)
    • Balanced but opposite optimization constant

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