We discussed RDC check in previous post. In this post, we will cover some common RDC techniques that help to avoid RDC violations:

  1. If the destination flop is a synchronizer, then this RDC path can immune from metastability
  2. If the destination flop is clock gated when reset to source flop is asserted, then there will be no metastability issues
  3. If the destination flop is already under reset when source flop is under reset, then there will be no RDC issues
  4. If the destination flop is power down when source flop is under reset, then there will be no RDC issues
  5. If the write enable of the destination flop is 0 when source flop is under reset, then RDC issue can be avoided.
  6. If the source flop output already stays at reset value and is stable when reset asserts, then there will be no RDC violations in destination flop

Asynchronous FIFO requires special handling in RDC, since read side and write side have independent clocks and resets. Typically, both sides of the asynchronous FIFO have to be reset at the same time. Assume read side gets reset but write side does not, write side may not generate correct “full” condition; similarly, assume write side gets reset but read side does not, then read side may not generate correct “empty” condition.

 

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