We discussed a general DC synthesis flow in previous post, and there are several things we need to check before actually running “compile_ultra”:
- Design should be fully read in by DC, and there shall be no black boxes or missing libraries
- Review linting issues, for example, no unexpected undriven inputs and outputs without loading, no bit width mismatch, no wire loop, no combo loop, etc.
- The SDC needs to be loaded correctly by DC, for example, use “report_timing_requirements -ignored” to check for invalid exceptions
- The SDC needs to be complete, for example, there is no missing clock, no un-clocked registers, no unconstrained ports, etc. Use “check_timing” command to check the completeness of SDC
- Optionally, designers can direct DC not to use ULVT / ELVT cells. This leaves more timing margin in place and route
Designers should check all listed items above, in order to get good synthesis results.
In some companies, such checks are performed automatically, and any error or warning will be captured in dashboards.