After setting up DC application variables and create milkyway library, we are ready for synthesis. The diagram below shows RTL synthesis flow in DC.

Read Design and Libraries

First we read in verilog file, and optionally DDC files. After specifying the top level design, it is always a good practice to do an explicit link and check if there is any sub-design unable to resolve. It is also recommended to check design hierarchy issues and make sure libraries are loaded correctly.

Here we used “redirect” command to save the reports to files.

Read Floorplan for DC-T

Read SDC

After loading the SDC, we should check if the completeness and correctness of SDC. There are a couple of DC commands that help with this.

Perform Synthesis

The actual synthesis starts with “compile_ultra” command, followed by scan insertion and optional incremental compile. It is a good idea to use path groups to apply more focus on critical paths, which we will discuss more in next post. Last step is to apply optional area recovery to the netlist.

Generate Reports

Usually, reports generation starts with “report_constriants” and “report_qor”. To report timing on individual paths, use “report_timing” command.

Save Results

The results can be saved in 3 different formats: gate-level netlist, mapped DDC file, and ICC2 file. How to generate these results are summarized below:

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