What are the common DC synthesis optimization techniques?

We have covered the basic DC synthesis flow in previous post. In synthesis, there are a couple of techniques that can help us improve the synthesis results:

Apply optimization directives as needed or as applicable
Apply appropriate compile options
Use path groups to apply more focus on critical paths
Incremental compile

Apply Optimization Directives

We listed a few optimization directives below:

1. High-Effort Timing Optimization: By default it is disabled; To enable it, do “set_app_var compile_timing_high_effort true”
2. Prioritizing setup timing over DRCs: By default DRCs have higher priority than timing during optimization. Otherwise, do “set_cost_priority -delay”
3. Disabling DRC fixes in clock network. Generally clock buffering prior to CTS is not desired; To disable DRC fixing on the entire clock network, do “set_auto_disable_drc_nets -on_clock_network true”
4. Test-ready synthesis is to account for area/timing impact of scan register during synthesis before stitching up scan chains; before synthesis, specify scan scheme by doing “set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | ssd | aux_clock_lssd>”, then do “compile_ultra -incremental -scan”
5. Multi-Core optimization. For example, do “set_host_options -max_cores 4”. To confirm host options, do “report_host_options“

Apply Compile Options

In “compile_ultra” command, we can optionally turn on the following 4 switches:

1. -spg: this option enables register replication for load balancing. By default, it does not consider loads across hierarchies. To enable register replication across hierarchies, do “set_app_var compile_register_replication_across_hierarchy true”
2. -retime: this option moves registers for potential timing critical paths. It is only targeted at reducing the WNS between non-pipelined registers.
3. -no_autoungroup: this option turns off auto-ungroup. By default, auto-ungroup is on, and it removes hierarchies of poorly partitioned sub-designers with IO paths violating timing
4. -no_boundary_optimization: this option turns off boundary optimization. By default, boundary optimization is on, and it maintains the hierarchy while performing complement propagation connects to compliment signal to reduce logic, constant propagation to remove redundant gates with time inputs, and unconnected pin propagation to remove redundant gates with unconnected outputs, etc.

Use Path Groups

Separating critical and sub-critical paths into different groups enables DC to optimize them independently. Usually, we have 4 path groups: input paths, output paths, reg-to-reg paths, and feedthroughs:

Incremental Compile

As we have seen in previous post, after the 1st pass synthesis, we can optionally apply incremental compile.