Why Do Designers Run Sanity Synthesis?
Before RTL designer hands the design over to synthesis / integration engineer, it will be a good idea to run some sanity synthesis. This is to make sure there is no lint errors, and no timing violations that can make timing closure impossible. We will cover more what to check before running synthesis in next post.
Sometimes people refer sanity synthesis to be Zero-Wire-Load / ZWL synthesis as well. Before looking at ZWL, it is worthy of understanding Wire Load Model.
What is Wire Load Model?
There are 2 modes available for estimating interconnect delays: Wire Load Model / WLM, or Topographical. WLM mode does not have physical view of the design, while Topographical mode has physical awareness.
WLM mode calculates the exact same R and C for all nets, but the interconnect delays will likely be over- or under-estimated. Therefore, the generated netlist will contain over- and under-buffered gates. At later time, the netlist may require additional iterations with physical design tools.
When doing the ZWL synthesis, there will be no RC delays counted by the tool. Thus designers use more pessimistic clock uncertainty to compensate.
We recommend interviewees to understand the concepts of WLM and ZWL. In next post, we will cover the production or topographical synthesis flow.