Due to the complexity and magnitude of state-of-the-art FPGAs, we as designers started imposing a higher-level structure on building designs. In turns that FPGAs designs and implementations are often composed of different cores or IP modules.
I/O interface cores, are typically implemented as structural RTL, usually with additional timing constraints which describe the timing relationships between signals and the variability of these signals. Such constraints shall also consider the interference of signals propagating through traces in the circuit board and connectors outside the chip. Usually, for high speed, such cores specifically make use of dedicated logics which is close to the I/O pins.
Along with I/O pins, FPGAs designs contain standard modules/cores, such as processor cores, on-chip memories, and interconnect switches.
Last but not least, FPGAs designs typically contain customized, application-specific accelerator modules/cores which are mainly synchronous logics.
One methodology is to regard HLS-generated accelerator modules like standard modules. After creating the appropriate accelerator modules through HLS, the modules are composed together along with I/O interface cores and standard modules to complete the design.