If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:
“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.
For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.
“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.
“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.
Let’s consider a simple example below, where clock mux for “CLK1” and “CLK2” resides in the design, and these 2 clocks are mutually exclusive.
Since accurate crosstalk-induced delay analysis is required, we can use “set_case_analysis”, “set_false_path”, or “set_clock_groups -logically_exclusive”.
# solution 1: use timing modes to verify timing
# mode 1
set_case_analysis 1 [get_ports SEL]
# mode 2
set_case_analysis 0 [get_ports SEL]
# solution 2: use false path
set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]
set_false_path -from [get_clocks CLK2] -to [get_clocks CLK1]
# solution 3: use logically exclusive
set_clock_groups -logically_exclusie -group CLK1 -group CLK2
What if, the clock mux resides outside of the design? Then we do not consider SI effect anymore, thus physically exclusive shall be used.
# use physically exclusive
set_clock_groups -physically_exclusive -group CLK1 -group CLK2
In large designs, there may be hundreds or thousands of clocks. Specifying “set_clock_groups” for mutually exclusive clocks is cleaner and easier to maintain. If using “set_fase_path”, each exclusive clock pair will need 2 constraints, then number of constraints will grow exponentially!