If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:

set_case_analysis
set_false_path
set_clock_groups -logically_exclusive
set_clock_groups -physically_exclusive

“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.

For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.

“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.

“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.

Let’s consider a simple example below, where clock mux for “CLK1” and “CLK2” resides in the design, and these 2 clocks are mutually exclusive.

Since accurate crosstalk-induced delay analysis is required, we can use “set_case_analysis”, “set_false_path”, or “set_clock_groups -logically_exclusive”.

What if, the clock mux resides outside of the design? Then we do not consider SI effect anymore, thus physically exclusive shall be used.

In large designs, there may be hundreds or thousands of clocks. Specifying “set_clock_groups” for mutually exclusive clocks is cleaner and easier to maintain. If using “set_fase_path”, each exclusive clock pair will need 2 constraints, then number of constraints will grow exponentially!

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