We have covered single-clock design constraints for Pre-CTS run and Post-CTS run. In this post, we will look at a more interesting scenario: constraining multi-synchronous-clock design.

How to Constrain Multiple Clock Input Delay?

Let’s assume, the design uses clock “CLKC” with period of 2ns, and the register driving the inputs of the design uses clock “CLKB” with period 3ns. Both “CLKC” and “CLKB” are divided from the same reference clock.

Thus we can define “CLKC” as master clock and “CLKB” as virtual clock to the design, and set input delay accordingly.

The diagram below shows how synthesis / STA tool try to close timing. There are 2 possible timing paths, and tool will try to close timing with tighter constraints.

How to Constraint Multiple Clock Output Delay?

Let’s assume, the design uses clock “CLKC” with period of 2ns, and outputs of the design drives registers clocked by either “CLKD” or “CLKE”. The period of “CLKD” is 1.33ns, and the period of “CLKE” is 1ns. Let’s further assume “CLKC”, “CLKD” and “CLKE” are divided from the same reference clock.

We can define “CLKC” as the master clock, and “CLKD” and “CLKE” as virtual clock to the design, and set output delay accordingly.

Note, without “-add_delay” option, the 2nd “set_output_delay” will override the 1st one, which is not desired. We want tool to consider both clocks and to constrain the output logic path to meet timing for both constraints.

The diagram below shows how synthesis / STA tool will try to close timing for the constraints above. Timing closure between “CLKC” and “CLKE” is relatively easy, since there is only one possible timing paths. There are 2 possible timing paths between “CLKC” and “CLKD”, and the tool will try to close timing with tighter constraints.

How to Specify Inter Clock Uncertainty?

When we specify clock uncertainty shown below, only capture clock uncertainty is applied.

To specify inter clock uncertainty, use the constraint below. The constraint below assumes combined effect of skew, jitter and margin are estimated to reduce the “effective clock period” from CLK1 to CLK2 by 0.1.

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