We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

The next step is to define generated clock. Generated clock is defined in hierarchical pins inside the design.

Remember, the source latency of the generated clock equals to master clock source latency + master clock network latency + sequential logic / macro internal latency; the network latency of the generated clock equals to estimated delay from FF1/out to register clock pins.

If you recall previous post, when we set multiple synchronous clock input delay, “CLKB” and “CLKC” are considered to be generated clocks of the reference clock; when we set multiple synchronous clock output delay, “CLKC”, “CLKD” and “CLKE” are considered to be generated clocks of the reference clock as well.

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