In previous post, we introduced how to manipulate objects in SDC. In this post, we will look at how to constrain single-clock design in synthesis, or Pre-CTS run. Note, there are some differences about how to set single-clock constraints in PnR, or Post-CTS run, and we will cover this topic in another post. Interviewees should not mix Pre-CTS and Post-CTS clock constraints.

First, we define the clock and its associated attributes, including clock period, waveform, name, and clock ports. If the clock duty cycle is not 50%, and both negedge and posedge are used in the design, then defining clock waveform is critical. This step is the same between Pre-CTS and Post-CTS run.

Next step is to model the clock uncertainty, which includes clock skew, jitter and margins. This clock uncertainty is usually set pessimistically, to leave more margin in PnR (see this post for more detail).

Then we want to model the clock latency, which includes clock source latency and clock network latency. Clock source latency models the delay from the actual clock source to the clock pin or port where the clock is defined.

Clock network latency models the delay from clock port / pin to the sink pin of registers.

The last step is to set clock rise and fall transition.


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