In previous post, we introduced how to manipulate objects in SDC. In this post, we will look at how to constrain single-clock design in physical design, or Post-CTS run. Note, there are some differences about how to set single-clock constraints in synthesis, or Pre-CTS run, and we will cover this topic in another post. Interviewees should not mix Pre-CTS and Post-CTS clock constraints.

First, we define the clock and its associated attributes, including clock period, waveform, name, and clock ports. If the clock duty cycle is not 50%, and both negedge and posedge are used in the design, then defining clock waveform is critical. This step is the same between Pre-CTS and Post-CTS run.

Next step is to model the clock uncertainty, which includes clock skew, jitter and margins. This clock uncertainty is usually set less pessimistically compared to Pre-CTS run. There is no need to model clock skew anymore, and clock skew is calculated from the real PnR netlist.

Then we want to model the clock latency. Unlike Pre-CTS run, this clock latency only include the clock source latency, and clock network latency will be extracted from PnR netlist by STA tool.

We use “set_propagated_clock” command to calculate clock network latencies inside the current design. We recommend to propagate the clock with “[get_ports CLK]” instead of [get_clocks CLK], to avoid propagating I/O reference clock. We will cover more in next post.

Unlike Pre-CTS run, we do not specify clock rise and fall transition time, since these are derived from PnR netlist as well.

 

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