by In previous post, we introduced how to manipulate objects in SDC. In this post, we will look at how to constrain single-clock design in physical design, or Post-CTS run. Note, there are some differences about how to set single-clock constraints in synthesis, or Pre-CTS run, and we will cover this topic in another post. Interviewees should not mix Pre-CTS and Post-CTS clock constraints.
First, we define the clock and its associated attributes, including clock period, waveform, name, and clock ports. If the clock duty cycle is not 50%, and both negedge and posedge are used in the design, then defining clock waveform is critical. This step is the same between Pre-CTS and Post-CTS run.
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# Waveform matters if both negedge and posedge of the clock are used in the design create_clock -period 2 -waveform {0 0.5} -name CLK [get_ports clk] |
Next step is to model the clock uncertainty, which includes clock skew, jitter and margins. This clock uncertainty is usually set less pessimistically compared to Pre-CTS run. There is no need to model clock skew anymore, and clock skew is calculated from the real PnR netlist.
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# Model clock jitters + margin; note no need to model skew set_clock_uncertainty -setup Tu [get_clocks CLK] |
Then we want to model the clock latency. Unlike Pre-CTS run, this clock latency only include the clock source latency, and clock network latency will be extracted from PnR netlist by STA tool.
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# Model latency or insertion delay; note no need to model network latency in post layout # Source latency models the delay from the actual clock origin to the create_clock port or pin set_clock_latency -source -max 3 [get_clocks CLK] |
We use “set_propagated_clock” command to calculate clock network latencies inside the current design. We recommend to propagate the clock with “[get_ports CLK]” instead of [get_clocks CLK], to avoid propagating I/O reference clock. We will cover more in next post.
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# Actual propagated clock network latencies are calculated inside the current design, while estimated ideal clock network latencies still apply to I/O reference clock set_propagated_clock [get_ports CLK] |
Unlike Pre-CTS run, we do not specify clock rise and fall transition time, since these are derived from PnR netlist as well.
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