Specifying only clock constraints is not enough for timing analysis. STA tool needs to understand the timing information with each input or output port. Note, there are slight differences about how to set interface constraints in Post-CTS run, and we will cover those in another post.

How to Specify Input / Output Delay?

The following example shows how to specify input port delay as if the input port is driven by a register.

The following example shows how to specify output port delay as if the output port drives a register.

Note, “set_input_delay” and “set_output_delay” will inherit the master clock’s source latency and network latency in the delay calculation. By default, the delay value specified in “set_input_delay” and “set_output_delay” does not include clock latencies.

If we want to handle different I/O clock latency from master clock latency, we can include different clock latencies in “input_delay” and “output_delay”, with “-source_latency_included” and “-network latency_included” options turned on.

Or, more commonly, we can create virtual clock copies of the master clock.

How to Specify Virtual Clock in Input / Output Delay?

The following example shows how to specify virtual clock I/O reference latencies.

“Input_delay” and “output_delay” are required but not sufficient for accurate timing analysis and optimization of IO logic paths. There are additional constraints we need to specify. Remember a gate’s delay depends on output load and input slew.

How to Specify Output Loads and input Transition Time?

The following example shows how to specify output loads and input transition times.

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