Specifying only clock constraints is not enough for timing analysis. STA tool needs to understand the timing information with each input or output port. Note, there are slight differences about how to set interface constraints in Pre-CTS run, and we will cover those in another post.

How to Specify Input / Output Delay?

The following example shows how to specify input port delay as if the input port is driven by a register.

The following example shows how to specify output port delay as if the output port drives a register.

Note, “set_input_delay” and “set_output_delay” will inherit the master clock’s source latency in the delay calculation. By default, the delay value specified in “set_input_delay” and “set_output_delay” does not include clock latencies.

If we want to handle different I/O clock latency from master clock latency, we can include different clock latencies in “input_delay” and “output_delay”, with “-source_latency_included” and “-network latency_included” options turned on.

Or, more commonly, we can create virtual clock copies of the master clock.

How to Specify Virtual Clock in Input / Output Delay?

The following example shows how to specify virtual clock I/O reference latencies. Note, we do not specify clock network latency for master clock in Post-CTS run.

How to Avoid Propagating IO Reference Clocks?

In previous post, we mentioned that actual propagated clock network latencies are calculated inside the current design, and we shall use “set_propagated_clock [get_ports CLK]”.

If we do “set_propagated_clock [get_clocks CLK]”, then I/O reference clocks also become propagated, but there are no actual clock paths, thus calculated I/O clock latencies are 0.

To avoid this, we can always do “set_propagated_clock” with “get_ports”; or if we have to do “set_propagated_clock” with “all_clocks”, we can create virtual clock for input/output delays and specify the source/network latency value on it. STA tool will preserve clock latency values specified for virtual clocks during propagation.

How to Specify Output Loads and input Transition Time?

“Input_delay” and “output_delay” are required but not sufficient for accurate timing analysis and optimization of IO logic paths. There are additional constraints we need to specify. Remember a gate’s delay depends on output load and input slew

The following example shows how to specify output loads and input transition times.

Sometimes STA engineers do not specify output loads and input transition times when closing block level timing. This is because, block level interface timing will be addressed in full-chip level STA.

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