Synthesis and STA tools will try to close timing between synchronous clocks, thus the tools need to know what clocks or paths are asynchronous, thus no timing closure is needed.
There are 2 ways to specify asynchronous design constraints. The first one is to use exceptions, i.e., specify “false path”. Even though intuitive and convenient, this approach is not recommended. If the path is not defined correctly and precisely, it may lead to unwanted “false path” where timing closure is required.
The more preferred approach is to use “set_clock_groups -asynchronous” command. In addition, this command still considers SI or noise analysis with infinite timing window. Thus this command is a more closer modeling to real silicon.