Verilog uses “x” to model the unknown state, but it also introduces potential issues.

The simulation semantics of conditional constructs in Verilog, are not accurate enough to model the ambiguity inherent in un-initialized registers and power on reset values. When the unknown states that are modeled as ‘X’ values become control expressions, these issues are particularly problematic.

In this post, we will cover several techniques to detect and resolve x-related issues in RTL, including:

Jasper Reset
SystemVerilog Assertions / SVA
Gate Level Simulation
X-propagation in RTL Simulation

Jasper Reset

Jasper is a formal toolkit, developed by Cadence. Jasper Reset is a tool to identify un-initialized registers in the design.

Jasper reset will generate a report, listing all registers that are not reset, and designers can check whether it is intended or not.

SystemVerilog Assertions / SVA

Designers can embed SystemVerilog Assertions, or SVAs in RTL, to check unintended “x” during simulation. The following is an example, showing data should not be “x” when valid is high.

Gate Level Simulation

The “x” issue can be detected in gate-level simulations, and often many gate-level simulations must be run only to debug X-related issues. However, gate-level simulation takes a long time to finish. Therefore, nowadays, people are enabling x-propagation in RTL to expedite this process.

X-propagation in RTL Simulation

Many RTL simulation tool support this feature. Readers can refer to this page to learn more about how VCS enables x-propagation.

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