After PnR netlist is ready, STA engineers needs to do timing verification and perform timing ECO as needed. In this post, we will cover the timing ECO procedure, and some common timing fix techniques. A typical timing ECO procedure is shown in the diagram below:

Timing ECO Procedure

DRC Fixes

Design Rule Checks, or DRC, usually refer to max transition and max capacitance limits set either by the timing library, or by designers. DRC fixes are the first step for timing ECO, since this prevents any extrapolation while computing the cell delay from timing library look-up table. Otherwise, the delay values reported by STA tools are not accurate and not reliable.

Note, clock path DRC fix has higher priority over data path DRC fix.

Setup Time Fixes

Setup time fixes are performed before hold time fixes, because this allows more timing margin for hold time fixes. Some hold time fix techniques are essentially borrowing timing slacks from setup time.

There are several ways for setup time fix:

  1. Vt swap
  2. Cell upsizing
  3. Sizing cells on side branch
  4. Clock skew adjustment

The first three techniques are straightforward, and the last one is worth some discussion.

Clock skew adjustment means borrowing timing slacks from later stage or previous stage. Borrowing timing slack from later stage requires delaying the clock at the capture flop; borrowing timing slack from previous stage requires removing clock buffers of launch flop.

Usually there is less room to play with by borrowing timing slack from previous stage, because this is bounded by how many clock buffers in launch clock path.

Hold Time Fixes

Some of hold time fixes are essentially opposite to setup fixes, for example:

  1. Vt swap
  2. Cell downsizing
  3. Add dummy load or upsize cells on side branch

These techniques are “trading” setup time for hold time slack.

There is one more technique that is specific to hold fix: buffer insertion. Designers need to be cautious about where to insert the buffers:

  1. Inserting buffers at common point, results in optimal number of buffers needed to fix hold time; however, this may impact setup time
  2. Inserting buffers at endpoint, results in more number of buffers being inserted; however, hold time fix rate will be more predictable and deterministic, as impact on setup time would be minimal

Noise Fixes

Noise fixes shall be the last step of timing ECO since noise is very sensitive and designers cannot afford to fix noise at each and every stage of timing ECO. Remember, any ECO change will impact the timing windows and overall noise pictures.

Conclusion

The timing ECO procedure and related timing fix techniques are widely covered in hardware interview questions. Other than STA engineers and physical design engineers, this topic is often used to test designers’ understanding towards timing.

In next post, we will talk about common timing ECO tools.

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