We used the example below to explain how derate / OCV works in PrimeTime. An interesting corner case is that, in both setup time and hold time analysis, cell u0 is subject to different derating. Obviously, this introduces unnecessary pessimism in timing analysis. PrimeTime introduces a concept called Clock Reconvergence Pessimism Removal, or CRPR, to address this issue.
A Formal Definition of CRPR
Clock Reconvergence Pessimism, or CRP, is the difference in delay along the common part of the launching and capturing clock paths. It assumes the shared segment has a min delay for one path and a max delay for the other.
This is an undesired effect due to the limitation of STA tool. The removal of this pessimism is called CRPR.
A CRPR Example
We will show a CRPR example based on previous post.
In setup timing analysis, the CRP for u0 = 0.1 x (1 + 10%) – 0.1 x (1 – 10%) = 0.02ns. By doing CRPR, setup timing slack increases from 0.23ns to 0.25ns.
In hold timing analysis, the CRP for u0 = 0.1 x (1 + 10%) – 0.1 x (1 – 10%) = 0.02ns. By doing CRPR, hold timing slack increases from 0.07ns to 0.09ns.
Actual CRPR in PrimeTime
In the example above, CRP for both setup time and hold time analysis is 0.02ns. However, for the same path, PrimeTime will not report the same CRP for setup and hold. Can you explain why is that?
A hint: setup time checks against different clock edges while hold time checks the same clock edge.
We have covered important concepts in PrimeTime in this post and previous posts. Starting from next post, we will discuss how to write timing constraints, which is also a popular topic in hardware interview.