In manufacture, chips on the same die may suffer from variations due to process, voltage or temperature change, thus transistors can be faster or slower in different dies. To compensate the variation, STA introduces a concept called On Chip Variation, or OCV. During design time, extra timing margins are added in timing analysis.

OCV has been evolved to Advanced OCV / AOCV, or even Parametric OCV / POCV. In this post, we will cover these three concepts.


In OCV, all cells or nets in launch clock path, data path and capture clock path will be added a fixed derate value, bringing more pessimism in timing analysis and compensating the variation.

We will cover how OCV is reflected in delay calculation in next post.


In real world, variations are rarely constants. Blindly adding a fixed derate value not only makes it hard for timing convergence, but also increases unnecessary area and power.

Variations usually follow Gaussian distribution: the more levels of logic a path has, the closer its variation follows Gaussian distribution, and the less variation the path has.

AOCV is represented by a 2-dimensional table: the derate value of a cell is determined by logic depth and distance. We have already seen how to read AOCV table in PrimeTime flow in previous post.


POCV models a cell delay using Gaussian distribution directly, instead of adding a derate value. Cell delay is calculated from a “parameter”, which is extracted from either library, or POCV table.

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