by Write a single Verilog module describing 5-to-1 multiplexer. Write a testbench using -2, -1, 0, 1, 2 for the five inputs of the multiplexer respectively, and apply appropriate values to the select lines to pass these inputs to the output.
Diagram
Design 1 – dataflow model
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module mux5to1 (input [2:0] din0, din1, din2, din3, din4, input [2:0] s, output [2:0] dout); wire [2:0] t1, t2, s3; assign t1 = s[0] ? din1 : din0; assign t2 = s[0] ? din3 : din2; assign t3 = s[1] ? din2 : din1; assign dout = s[2] ? din4 : t3; endmodule |
Design 2 – behavioral model
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module mux5to1 (input [2:0] din0, din1, din2, din3, din4, input [2:0] s, output reg [2:0] dout); reg [2:0] tmp1, tmp2, tmp3; always @ * begin if (s[0]) tmp1 = din1; else tmp1 = din0; if (s[0]) tmp2 = din3; else tmp2 = din2; if (s[1]) tmp3 = tmp2; else tmp3 = tmp1; if (s[2]) dout = din4; else dout = tmp3; end endmodule |
Testbench
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`timescale 1ns/1ns module tb_mux5to1; reg [2:0] din0, din1, din2, din3, din4; reg [2:0] s; wire [2:0] dout; integer i; mux5to1 CP_MUX (.din0(din0), .din1(din1), .din2(din2), .din3(din3), .din4(din4), s(s), .dout(dout)); initial begin din0 = 3'b110; din1 = 3'b111; din2 = 3'b000; din3 = 3'b001; din4 = 3'b010; for (1=0; i<=4; i=i+1) begin s = i; #5; end $finish; end endmodule |
I think the Design 1 is wrong
Why
Hi, I think it’s just a typo in the dout assignment
In the first design, line 8 (assign t3 = s[1] ? din2 : din1;) should be: assign t3 = s[1] ? t2 : t1;
In the first design, line 8 (assign t3 = s[1] ? din2 : din1;) should be: assign t3 = s[1] ? t2 : t1;