Write a single Verilog module describing 5-to-1 multiplexer. Write a testbench using -2, -1, 0, 1, 2 for the five inputs of the multiplexer respectively, and apply appropriate values to the select lines to pass these inputs to the output.

Diagram

Design 1 – dataflow model

Design 2 – behavioral model

Testbench

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6 Comments

  1. In the first design, line 8 (assign t3 = s[1] ? din2 : din1;) should be: assign t3 = s[1] ? t2 : t1;

  2. In the first design, line 8 (assign t3 = s[1] ? din2 : din1;) should be: assign t3 = s[1] ? t2 : t1;

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