We talked about using “check_timing” command in PrimeTime, to verify completeness and correctness of SDC. However, as runtime becomes longer and longer, STA team cannot afford wasting time running PrimeTime using “incomplete” or “incorrect” SDC. We need to have way to “verify” SDC before invoking PrimeTime. The most common tool is FishTail.
What Does FishTail Verify?
The table below shows a few items that FishTail will check against SDC. Usually, STA team wants to make sure FishTail verification passes before invoking PrimeTime.
|Clock Definition||Un-clocked registers|
|Clock Definition||Clocks defined on hierarchical pins|
|Clock propagation||Reconvergent clocks|
|Clock propagation||Clock propagating through non-unate cells whose side-inputs are not set to a constant value|
|Clock propagation||False path in clock generation logic that prevents STA tool from propagating the clock|
|Generated clocks||Generated clock has no master clock|
|Generated clocks||Generated clock blocks the propagation of other clocks|
|Generated clocks||Generated clock has incorrect edge specification|
|Clock groups||Incorrect logically or physically exclusive clock groups|
|Clock groups||Incorrect clock-to-clock exceptions|
|Clock groups||Missing clock groups|
|Clock-to-clock false path||Missing timing exceptions between clocks with non-integer clock periods|
|IO delays||Missing input / output delays|
|IO delays||Propagation of conflicting constant values to the same pin|
|Case analysis||Case analysis values specified on multiple combo pins cannot be simultaneously satisfied|
|Non-clock-to-clock false path between synchronous clocks is specified correctly for setup timing check|
|Prove when a startpoint transitions, this change cannot propagate to the endpoint in less than number of clocks cycles specified by user|
|A setup multi-cycle-path shall accompany with a hold multi-cycle-path|
|A hold shift is less than setup shift – 1|