by Design a parameterized fix-point adder with assignable inputs and outputs bitwidth:
Input 1 – Integer Bits: WI1, Fractional Bits: WF1
Input 2 – Integer Bits: WI2, Fractional Bits: WF2
output – Integer Bits: WIO, Fractional Bits: WFO
output – OVF (overflow signal)
Modern digital signal processors (DSPs) and microprocessors may involve high-precision digitized representation of real values. No finite number system can represent any real value. A sequence of n bits in a register can represent an integer and/or a fractional number. Any real value could be separated into an integer part and a fractional part. The delimitation of the integer part and the fractional part is called the radix point. There are two systems that can be used to represent a subset of real numbers: fixed-point format and floating-point format. In hardware implementation of the fixed-point format, the radix point is implied in a pre-determined fixed position. The wordlength and the position of the radix point are two main attributes of the fixed-point format. The n bits are separated into two parts: i bits for the integer part and f bits are used for the fractional part.
Design
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`timescale 1ns / 1ps module fixPointAdder # (parameter WI1 = 4, //length of the integer part, operand 1 WF1 = 3, //length of the fraction part, operand 1 WI2 = 6, //length of the integer part, operand 2 WF2 = 5, //length of the fraction part, operand 2 WIO = 1, WFO = 15 ) (input CLK, RST, input signed [WI1+WF1-1 : 0] in1, input signed [WI2+WF2-1 : 0] in2, output reg signed [WIO+WFO-1 : 0] out, output reg OVF); parameter intL = ((WI1>=WI2)?WI1:WI2); //integer length of correct results parameter frcL = ((WF1>=WF2)?WF1:WF2); //fraction length of correct results reg signed [intL+frcL-1 : 0] tmp; //The output with correct number of bits reg [WIO-1 : 0] outI; //The integer part of the output reg [WFO-1 : 0] outF; reg signed [intL+frcL-1 : 0] o1, o2; //variable that could be execute in behavioral module always @ * begin if (WI1>=WI2) begin //Situation1 WI1>=WI2 WF1>=WF2 if (WF1>=WF2) begin o1 = in1; o2 = { {(WI1-WI2){in2[WI2+WF2-1]}}, in2, {(WF1-WF2){1'b0}} }; end else begin //Situation2 WI1>=WI2 WF1<WF2 o1 = { in1, {(WF2-WF1){1'b0}} }; o2 = { {(WI1-WI2){in2[WI2+WF2-1]}}, in2}; end end else begin if (WF1>=WF2) begin //Situation3 WI1<WI2 WF1>=WF2 o1 = { {(WI2-WI1){in1[WI1+WF1-1]}}, in1 }; o2 = { in2, {(WF1-WF2){1'b0}} }; end else begin //Situation4 WI1<WI2 WF1<WF2 o2 = in2; o1 = { {(WI2-WI1){in1[WI1+WF1-1]}}, in1, {(WF2-WF1){1'b0}} }; end end end always @* tmp = o1 + o2; //--------------------adjusting the bitwidth for the fractional part---------------------------------------------------------- always @* begin if (WFO >= frcL) //append 0s to the lsb bits outF = {tmp[frcL-1:0] , {(WFO-frcL){1'b0}}}; else //WFO<(WF1+WF2): Truncate bits from the LSB bits outF = tmp[frcL-1 : frcL-WFO]; end //--------------------adjusting the bitwidth for the integer part------------------------------------------------------------- parameter X_trc = (WIO>=2)? (WIO-2+frcL) : frcL; always @* begin if (WIO>=intL) //sign extend the integer part if (OVF==0) outI = {{(WIO-intL){tmp[intL+frcL-1]}}, tmp[intL+frcL-1:frcL]}; else outI = {{(WIO-intL){~tmp[intL+frcL-1]}}, tmp[intL+frcL-1:frcL]}; else begin //WIO<(WI1+WI2) if (WIO==1) outI = tmp[intL+frcL-1]; else //outI = `X_trc; outI = {tmp[intL+frcL-1], tmp[X_trc:frcL]}; //outI = { tmp[intL+frcL-1], tmp[WIO-2+frcL:frcL]}; //truncate bits from the MSB part but keep the sign bit end end //--------------------registering the output---------------------------------------------------------------------------------- always @ * begin //(posedge CLK) if (!RST) out <= 0; else out <= {outI [WIO-1:0], outF [WFO-1:0]}; end //--------------------Overflow Detection-------------------------------------------------------------------------------------- always @* begin if(in1[WI1+WF1-1]==in2[WI2+WF2-1]) OVF = in1[WI1+WF1-1]^tmp[intL+frcL-1]; else OVF = 0; end endmodule |
Testbench
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`timescale 1ns / 1ps module tb_fixpoint_adder; // Inputs reg CLK, RST; reg [8:0] in1; reg [9:0] in2; //Inputs of case 1 // Outputs wire [10:0] out1; wire [12:0] out2; wire [16:0] out3; wire [14:0] out4; //ovf wire OVF1,OVF2,OVF3,OVF4; //Real Number Presentation real in1_real, in2_real, out1_real, out2_real, out3_real, out4_real; real floatout1; //floating number results // ================================Function Definition==================================// function real fixedToFloat; input [63:0] in; input integer WI; input integer WF; integer idx; real retVal; begin retVal = 0; for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin if(in[idx] == 1'b1) begin retVal = retVal + (2.0**(idx-WF)); end end fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1))); end endfunction // ======================================================================================// //====================================Initialization=====================================// // Instantiate the Unit Under Test (UUT) for Case 1 // WIO=max(WI1+WI2), WFO=(WF1+WF2); fixPointAdder #( .WI1(5), //length of the integer part, operand 1 .WF1(4), //length of the fraction part, operand 1 .WI2(7), //length of the integer part, operand 2 .WF2(3), //length of the fraction part, operand 2 .WIO(7), //default length for the integer part of the required output .WFO(4)) Fang_utt_Case1 (.CLK(CLK), .RST(RST), .in1(in1), .in2(in2), .out(out1),.OVF(OVF1)); // Instantiate the Unit Under Test (UUT) for Case 2 // WIO=max(WI1+WI2)+1, WFO=(WF1+WF2)+1; fixPointAdder #( .WI1(5), //length of the integer part, operand 1 .WF1(4), //length of the fraction part, operand 1 .WI2(7), //length of the integer part, operand 2 .WF2(3), //length of the fraction part, operand 2 .WIO(8), //default length for the integer part of the required output .WFO(5)) Fang_utt_Case2 (.CLK(CLK), .RST(RST), .in1(in1), .in2(in2), .out(out2),.OVF(OVF2)); // Instantiate the Unit Under Test (UUT) for Case 3 // WIO<max(WI1+WI2), WFO<max(WF1+WF2); fixPointAdder #( .WI1(5), //length of the integer part, operand 1 .WF1(4), //length of the fraction part, operand 1 .WI2(7), //length of the integer part, operand 2 .WF2(3), //length of the fraction part, operand 2 .WIO(1), //default length for the integer part of the required output .WFO(15)) Fang_utt_Case3 (.CLK(CLK), .RST(RST), .in1(in1), .in2(in2), .out(out3),.OVF(OVF3)); // Instantiate the Unit Under Test (UUT) for Case 4 // WIO>max(WI1+WI2)+1, WFO>max(WF1+WF2)+1; fixPointAdder #( .WI1(5), //length of the integer part, operand 1 .WF1(4), //length of the fraction part, operand 1 .WI2(7), //length of the integer part, operand 2 .WF2(3), //length of the fraction part, operand 2 .WIO(9), //default length for the integer part of the required output .WFO(6)) Fang_utt_Case4 (.CLK(CLK), .RST(RST), .in1(in1), .in2(in2), .out(out4),.OVF(OVF4)); //=========================================================================================// // clock generator parameter ClockPeriod = 10; initial CLK = 0; always # (ClockPeriod/2) CLK = ~CLK; //====================================Initialize Inputs====================================// parameter Testdada_Deph = 12; parameter Testdata_Bits = 19; reg [Testdata_Bits-1:0] Testdata_vec [Testdada_Deph-1:0]; //The vector of the testdata integer count; initial begin $readmemb("fpTestdata.txt", Testdata_vec); RST = 0; @(posedge CLK); RST = 1; for (count=0; count<=Testdada_Deph; count=count+1) begin {in1, in2} = Testdata_vec[count]; if( out4_real == floatout1 ) $display("The %d clock cycle's value is matched", count); else $display("The %d clock cycle's value is mismatched <=====", count); @(posedge CLK); if (count==Testdada_Deph) $finish; end end //===================================Pesentation============================================// always @ in1 in1_real = fixedToFloat(in1, 5, 4); always @ in2 in2_real = fixedToFloat(in2, 7, 3); always @ out1 out1_real = fixedToFloat(out1, 7, 4); //Transfer the fix-point output1 to float point for case 1 always @ out2 out2_real = fixedToFloat(out2, 8, 5); //Transfer the fix-point output1 to float point for case 2 always @ out3 out3_real = fixedToFloat(out3, 1, 15); //Transfer the fix-point output1 to float point for case 2 always @ out4 out4_real = fixedToFloat(out4, 9, 6); //Transfer the fix-point output1 to float point for case 4 always @ (in1_real or in2_real) floatout1 = in1_real + in2_real; endmodule |
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