We discussed a general PrimeTime analysis flow in previous post, and there are several things we need to check before actually running “update_timing”:

  1. Design should be fully read in by PrimeTime, and there shall be no black boxes or missing libraries
  2. The netlist shall be accurately and completely annotated by SPEF, and there shall be no unannotated parasitics
  3. The netlist shall be accurately and completely annotated by AOCV table; if there exists unannotated cell, we should debug why
  4. The SDC needs to be read in correctly by PrimeTime, and there shall be no “unrecognized” SDC identified by PrimeTime
  5. The SDC needs to be complete, for example, there is no missing clock, no un-clocked registers, no unconstrained ports, etc.

Designers should check all listed items above, in order to achieve accurate STA results. To check #4 and #5 above, there exists a more sophisticated tool called FishTail, and we will cover later.

In some companies, such checks are performed automatically, and any error or warning will be captured in dashboard.

Another fundamental topic to understand is, GBA mode and PBA mode. We will cover these modes in next post.

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