Generally speaking, High-level synthesis (HLS) is a kind of abstraction which enables a chip/circuit design engineer to focus on overview of a large architectural problems instead of register level or cycle-to-cycle operating problems.

Instead of using RTL Language, HLS open use C/C++ as input languages. We’ve also noticed other explorations on even higher level scripting language like Python or Keras (Python ML Library) for even larger applications.

HLS will tackle the following tasks:

  • Analyzing the algorithmic concurrency
  • Inserting needed registers into designed circuits for specific timing requirements
  • Generating correspondent control logic circuits for directing the data path
  • Connecting the rest of the circuits parts with interfaces
  • Mapping data to storage blocks for balancing resource usage and bandwidth needs
  • Optimizing for resources and timing constraints

Overall, the main goal of HLS is to generate reference circuits automatically and swiftly according to user-provided design specifications and constraints.

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