In previous posts, we mainly focus on setup and hold time constraints. There are other types of timing constraints that STA should check. These checks include but not limited to:

Reset removal time and recovery time
Clock gating cell timing
Data to data timing

Reset Removal Time and Recovery Time

Usually an asynchronous reset has to be synchronized to achieve synchronous deassertion. Reset deassertion cannot be too closed to valid clock edges, otherwise it may cause metastability. This constraint is called reset removal time and recovery time, which is shown in the diagram below:

Reset deassertion must happen after reset removal time is met, but before entering recovery time window. If you recall setup time and hold time, removal time is similar to hold time while recovery time is similar to setup time.

STA should check all flops satisfy reset removal time and recovery time constraints.

Clock Gating Cell Timing

Clock gating cells are widely used in SoC design, as a power-saving method. A typical clock gating cell, shown in the diagram below, consists of a low level transparent latch and an AND gate. The existence of the latch is to make sure clock does not glitch when clock is high, but it also introduces additional timing checks.

STA needs to make sure the in1 becomes stable before next positive clock edge, i.e., setup time check has to be satisfied. STA also needs to guarantee that latch output change reaches AND gate after in2 is low, i.e., hold time constraint has to meet.

Data to Data Timing

Data to data timing check is to make sure data is stable relative to data valid. See the diagram below:

To be more specific, setup check is to make sure that data is stable before data valid asserts; hold check is to make sure that data is stable after data valid asserts.

Conclusion

In this post, we covered three special timing checks performed by STA. These timing checks are often used to check interviewee’s understanding toward STA. In particular, interviewees should memorize the launch and capture clock edges with respect to each timing check.

In next post, we will discuss an implicit timing check that is usually ignored in timing verification for asynchronous FIFOs.

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