Asynchronous FIFOs are widely used for clock domain crossing. Since STA is not used for asynchronous FIFO timing check, designers tend to naively leave asynchronous FIFOs unattended in STA and asynchronous FIFO functionality may break.

Asynchronous FIFO Assumption

There is a fundamental assumption about asynchronous FIFO: asynchronous FIFO pointers in source clock domain can only change 1 bit before synchronized to destination clock domain

Without special constraints, PnR tools may place different bits of the pointer far far away, thus multiple bits of pointers can change simultaneously from the views of synchronizers in destination clock domain.

Therefore, designers need to put constraints to control skews among different bits of the FIFO pointer.

How to Constrain Skews of Pointer Bits

If the pointers get updated every cycle, then the skew between bits must be within a bit time or 1 source clock cycle; if the pointers get updated every other cycle, then this constraint can be relaxed to 2 bit time or 2 source clock cycles.


We recommend readers to refer to Paul Zimmer’s paper “No Man’s Land, Constraining Async Clock Domain Crossings” for more implementation details. Understanding how to constraint asynchronous FIFO pointers will definitely impress potential employers.

In next post, we will discuss how to check timing for latch based design.

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