In previous post, we discussed how to constrain asynchronous FIFO pointer in STA. In this post, we will cover how STA check latch based design.

**Why Do We Do Latch Based Design?**

Latch based design enables time borrowing, which is shown below.

Let say we want to finish computing logic A, B and C in 2 clock cycles, and none of these logic can be further divided. In pure flops based design, if both (A + B) and (B + C) take more than 1 cycle to finish, then it is impossible to close timing.

In latch based design, NEG LATCH separates logic A and B, and POS LATCH separates logic B and C. Now (A + B) can be relaxed to 1.5 cycles, and timing closure will be easier.

However, latch based design introduces more complexed timing analysis.

**How to Check Timing in Latch Based Design**

To check timing for logic A, see the diagram below. If logic A is able to finish in half cycle, then no time borrowing happens (Path I in the diagram); if logic A takes more than half cycle to complete, then there will be time borrowing (Path II in diagram).

In both cases, logic A has to meet setup time constraint for NEG LATCH2.

Check timing for logic B becomes tricker, due to possible time borrowing in logic A and B. See diagram below:

There are 4 cases to analyze:

- Logic A does not have time borrowing, but B has time borrowing (Path I in diagram)
- Logic A does not have time borrowing, and B does not have time borrowing either (Path II in diagram)
- Logic A has time borrowing, but B has time borrowing (Path III in diagram)
- Logic A has time borrowing, and B does not have timi borrowing either (Path IV in diagram)

In any of the cases above, logic A and B have to meet setup time constraint for POS LATCH3

Logic C timing check has 2 cases as well, see the diagram below. Path I in the diagram shows the case where B has time borrowing, and Path II in diagram shows the case where B does not have time borrowing.

In either case, logic B and C have to meet setup time constraint for FF4.

**Conclusion**

Flop based design has a very clear boundary where the timing check should be performed, because flops are edge triggered. Latch based design has more cases for timing check, since latches are level sensitive in nature, and it enables time borrowing between different stages. We recommend interviewees to fully digest the example in this post, and try to explain latch based design timing check in your own language.

In next post, we will start to dive into the most popular STA tool: PrimeTime.

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