What is STA?
Static Timing Analysis, a.k.a., STA, is timing verification methodology.
STA is exhaustive, since it uses formal, mathematical techniques instead of dynamic logic simulation, to perform analysis. STA will first identify all timing paths inside the design, and perform timing checks on all paths.
STA is also constraint driven, i.e., by default, it does not report a path that is not constrained for timing.
Unlike CDC, STA assumes all clocks and all paths are synchronous by default, and it will attempt to close timing for all synchronous paths. Designers need to specify asynchronous clocks or paths, where timing closure is not required.
What does “synchronous” mean?
You may wonder what “synchronous” really means in the context of timing verification. If the relationship between launch clock and capture clock is bounded, we call it “synchronous”. Some examples of “asynchronous” would be:
- Launch clock is 100MHz, while capture clock is 37MHz
- Launch clock and capture clocks do not share the same clock source, thus they don’t have different skew or jitter
- Launch clock tree capture clock tree are not balanced
Understanding the nature of STA establishes the baseline of STA. We highly recommend readers to fully digest this post before proceeding. In next post, we will discuss the basic timing constraints in STA: setup time and hold time.