You may already noticed that, in timing reports, there is an item called clock uncertainty. Clock uncertainty hurts both setup and hold timing closure. In this post, we will list out a couple of sources that introduce clock uncertainty.
Sources of Clock Uncertainty
The exact amount of clock uncertainty usually cannot be predicted beforehand. The sources of clock uncertainty include:
- Clock sources, e.g. PLL, have jitters in nature.
- Manufacturing device variations
- Changes of temperature during operation. The variation of temperature leads to variations of clock cell speeds.
- Power supply variations. The power rail will not always stay in the nominal voltage. For example, when more circuits are turned on and absorbing current, the voltage drop in supply rail will be higher.
- Changes of capacitive load. Capacitive load is nonlinear in nature and its value depends on the applied voltage. In addition, for latches and flops, their clock load is a function of the stored value
- Capacitive and cross-talk to adjacent wires
Modeling Clock Uncertainty
Usually, STA tools require designers to specify the clock uncertainty as a percentage of clock period. In ZWL synthesis or sanity synthesis, this value is more pessimistic. However, in timing verification of PnR netlist, designers use less pessimistic clock uncertainty but rely on OCV / AOCV to leave more timing margins in design.