As the SoC complexity increases significantly, silicon debug becomes more difficult. Without any special treatment, identifying the root cause of a chip failure would be impossible. Therefore, designers will need to apply several Design for Debug, or DFD techniques before taping out. These offers great visibilities towards silicon debug, and they are widely adopted in today’s SoC design. In this post, we will discuss several DFD techniques.
Exposing Internal States to Register Space
Exposing system internal states to register space is the most straightforward solution. These internal states include but are not limited to:
FIFO full / empty status
Credit counter status
Finite state machine status
One thing to remember is that, these internal states shall not be dynamic changing, since register access is usually slow. Dynamic changing states captured by register access can be stale and they do not reflect the system real-time status.
Security is also a concern, since hackers can get system internal states by accessing registers. Usually some “locking” and “hiding” mechanisms shall be implemented to protect these debug registers.
DFT engineers will insert scan chains in the chip while performing synthesis. The scan chains can be used for not only detecting stuck-at faults, but also dumping out “snapshot” of system states.
In scan shift phase, silicon validation engineers can pre-load desired stimulus; in scan capture phase, the failing point status can be captured, and shifted out for further analysis.
This approach is similar to making cartoons: each “snapshot” is a “frame”. Silicon validation engineers can analyze the system states “frame” by “frame”, until the failing reason is identified.
The drawback of this approach is that, the debug process may be slow, especially when long scan chain exists.
On Chip Trace Analyzer
An example of on chip trace analyzer is shown in the diagram below.
Usually, designers need to define some trigger events and trace data to dump. For example, a trigger event can be a “start” signal, and trace data can be the states of an FSM.
Once the trigger event happens, trace analyzer will start capturing trace data and store it in trace dump SRAM. The behavior of capturing trace data can be configured through registers.
Once the trace dump is stored in SRAM, it can either be read through register accesses, or sent to external memory. Storing trace dump to external memory can be useful, since trace dump SRAM has limited storage.
In this post, we discussed three widely used DFD techniques: exposing internal states to register space, scan dump and on chip trace analyzer. Although the concept is simple, silicon debug still requires the validation engineers to understand the system, come up with proper test plan, and analyze the results.