by The last step before taping out a chip is sign-off. Design leads and chip leads will need to fill in sign-off checklist item by item, making sure all required checks are complete.
In this post, we will show an example front end design checklist. Designers and verification engineers can use this as a reference. Students and interviewees can use this checklist to sharpen the understanding of front end design flow.
| Category | Checklist Item |
| Documentation Checklist | |
| Documentation | High-level Architecture Spec version and status |
| Documentation | Microarchitecture Spec version and status |
| Documentation | Latency, throughput and other performance numbers for functional modes |
| Documentation | Performance counters |
| Documentation | Major block diagrams and pipeline stages |
| Documentation | List of clocks and resets |
| Documentation | Reset sequence waveforms |
| Documentation | Flow control |
| Documentation | Low power features |
| Documentation | Reliability, accessibility and serviceability features |
| Documentation | Error status, interrupts and error handling flow |
| Documentation | Design for debug features |
| Documentation | Design statistics (flop counts, memory and other macros, latches, gate counts etc.) |
| RTL Coding Checklist | |
| RTL coding | All functional features implemented |
| RTL coding | All macros instantiated, e.g., SRAM |
| RTL coding | All interfaces/ports implemented and connected |
| RTL coding | All interfaces/ports connections reviewed |
| RTL coding | Assertion and coverage properties coded |
| RTL coding | Registers connected to functional logic |
| RTL coding | Reliability, accessibility and serviceability features coded |
| RTL coding | Error status, interrupts and error handling flow implemented |
| RTL coding | Design for debug features coded |
| RTL coding | DFT features coded |
| RTL coding | All code clean up completed (no “FIXME” or “TODO” left in the code) |
| RTL coding | All CDCs are handled properly |
| RTL coding | No VCS warnings |
| RTL coding | No “if-def” in RTL |
| RTL coding | All files checked in |
| RTL coding | One spare / ECO register implemented at the last address of the configuration address space |
| RTL coding | All cells on clock path should be from the common library, e.g., ICG |
| IP integration | |
| IP integration | Check production version of all internal & external IPs |
| IP integration | Check with IP vendor on post integration workarounds / ECOs or any other unimplemented features, if any |
| IP integration | Replace 3rd party primitive cells with common library cells |
| IP integration | IP integration reviewed with the all internal or external IP vendor |
| Linting Checklist | |
| Linting | Spyglass lint run reviewed and clean with waivers |
| Linting | BBOX modules reviewed |
| Linting | Confirm 0 errors and 0 warnings with waivers |
| Linting | ERROR waivers reviewed |
| Linting | WARNING waivers reviewed |
| CDC Checklist | |
| CDC | SGDC, clock, reset and all set up completed and logs reviewed |
| CDC | Structural verification completed and logs reviewed |
| CDC | Functional verification completed and logs reviewed |
| CDC | Spyglass CDC sign off run reviewed and clean with waivers |
| CDC | All waivers reviewed |
| RDC Checklist | |
| RDC | SGDC, clock, reset and all set up completed and logs reviewed |
| RDC | Spyglass RDC sign off run reviewed and clean with waivers |
| RDC | All waivers reviewed |
| Timing Constraints Checklist (Fishtail) | |
| SDC | Number of supported test modes aligned with SDC |
| SDC | Number of supported functional modes aligned with SDC |
| SDC | Functional mode(s) SDC created |
| SDC | Functional mode(s) SDC checked using Fishtail and results reviewed |
| SDC | Functional mode(s) exceptions checked and reviewed |
| SDC | Test mode(s) SDC created |
| SDC | Test mode(s) SDC checked using fishtail and results reviewed |
| SDC | Test mode(s) exceptions checked and reviewed |
| SDC | I/O issues report reviewed and clean |
| SDC | Un-clocked, unconstrained, half-cycle report reviewed |
| SDC | Clock generation/propagation issues report reviewed and clean |
| SDC | All waivers reviewed |
| Sanity / ZWL Synthesis Checklist | |
| Synthesis | Check_design reports have no errors |
| Synthesis | No unintended latches in the design |
| Synthesis | No errors in the log |
| Synthesis | All WARNING reviewed |
| Synthesis | Review clock/reset paths with physical design team |
| Synthesis | Number of registers reviewed and inline with expectations |
| Synthesis | Number of macros reviewed inline with expectations |
| DFT Checklist | |
| DFT | DFT ports inserted |
| DFT | All clock and reset controllables |
| DFT | All DFT features implemented |
| DFT | DFT rules checked and passing |
| DFT | Spyglass DFT DSM log reviewed |
| DFT | Waiver review |
| DFT | Test coverage reviewed |
| LEC – RTL vs ZWL Synthesis | |
| LEC | Review LEC setup |
| LEC | Zero nonequivalent points |
| LEC | BBOX count reviewed and waived |
| LEC | No IO mismatch |
| LEC | All unmapped – unreachable points reviewed and waived |
| LEC | All unmapped – extra points reviewed and waived |
| LEC | All unmapped – not mapped points reviewed and waived |
| Functional Verification Checklist | |
| Verification | Wave dump reviewed |
| Verification | Test plan reviewed and signed off |
| Verification | Regression with xprop completed and passing |
| Verification | Regression with synchronizer cycle slip model enabled completed and passing |
| Verification | PnR netlist simulated with SPEF run at SS/TT/FF corners |
| Verification Coverage Checklist | |
| DV Coverage | Regression includes all tests and run with random seeds |
| DV Coverage | Regression 100% passing |
| DV Coverage | Functional coverage plan reviewed and signed off |
| DV Coverage | Functional coverage 100% passing with waivers |
| DV Coverage | Functional coverage waivers reviewed and signed off |
| DV Coverage | Assertion plan reviewed and signed off |
| DV Coverage | Assertion 100% passing with waivers |
| DV Coverage | Assertion waivers reviewed and signed off |
| DV Coverage | Code coverage (line / toggle / FSM / branch) 100% with waivers |
| DV Coverage | Code coverage waivers reviewed and signed off |
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