by Case statement is usually used to model read-only memory (ROM). For some compiler or certain device family, either the address or the output has to be registered for ROM code to be inferred. block RAM resources could be used to implemented ROMs with synchronous outputs or address inputs.
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// Design a synchronous ROMs using BlockRAM module rom_sync # (parameter addressWidth = 3, dataWdith = 4) (input clk, en, input [addressWidth-1:0] address, output reg [dataWidth-1:0] dout); always @ (posedge clk) begin if (en) case (address) 3'b000: dout <= 4'b0010; 3'b001: dout <= 4'b0010; 3'b010: dout <= 4'b1110; 3'b011: dout <= 4'b1000; 3'b100: dout <= 4'b0100; 3'b101: dout <= 4'b1010; 3'b110: dout <= 4'b1100; 3'b111: dout <= 4'b0000; default: dout <= 4'bXXXX; endcase end endmodule |
Note:
Please create ROM blocks in a separate module which include only the ROM logics since you might need to treat the ROM as a black box.
Related Questions:
- Design a single-port synchronous RAM (Read first)
- Design a single-port synchronous RAM (Write first)
- Design single and dual-port asynchronous read RAM
- Design a dual-port RAM with two clocks from different clock domains
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