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// Design a dual-port RAM with two clocks from different clock domains module ram_dual_clock (input [15:0] din, input [4:0] address_in, input [4:0] address_out, input we, clk1, clk2, output reg [15:0] dout); reg [4:0] address_out_reg; reg [15:0] ram [31:0]; always @ (posedge clk1) begin if (we) ram[address_in] <= din; end always @ (posedge clk2) begin address_out_reg <= address_out; dout <= ram[address_out_reg]; end endmodule |
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