Similar as transmit a signal from slow to fast clock domain, a 2-stages register synchronizer is needed between fast and slow clock domains. As you are wandering, extra control logics is needed to hold the fast domain (source) on transmitting while slow (destination) domain is finishing processing. We call it “handshaking” mechanism which requires a handshaking signal from destination clock domain to the source clock domain telling when to be ready to send next signal.

The control logics can be implemented with a “pulse synchronizer”

Design a circuit to sync a signal from fast domain to a slow domain.png

When transmitting the signal O1, the controller logics is used for holding the output steady without changing into new value till it receives the “handshake” signal from the destination domain. The handshake signal will generate a rising edge pulse between O4 and O5 that represent the O2 is low again then the transmitter (source) side could start a new transmission.

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