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// Design a single-port asynchronous reading RAM module ram_writefirst #(parameter addressWidth = 5, dataWidth = 32) (input clk, we, en, input [addressWidth-1:0] address, input [dataWidth-1:0] din, output reg [dataWidth-1:0] dout); // Initialize the RAM reg [dataWidth-1:0] RAM [2**addressWidth-1:0]; always @ (posedge clk) begin if (en) begin if (we) RAM[address] <= din; end end assign dout = RAM[address]; endmodule |
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// Design a dual-port asynchronous reading RAM module ram_writefirst #(parameter addressWidth = 5, dataWidth = 32) (input clk, we, en, input [addressWidth-1:0] address1, address2, input [dataWidth-1:0] din, output reg [dataWidth-1:0] dout1, dout2); // Initialize the RAM reg [dataWidth-1:0] RAM [2**addressWidth-1:0]; always @ (posedge clk) begin if (en) begin if (we) RAM[address] <= din; end end assign dout1 = RAM[address1]; assign dout2 = RAM[address2]; endmodule |
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