Synchronization is an elementary aspect of designing. Interviewers usually assume that you have designed modules through multiple clock domains. Unfortunately, lots of new grads don’t have any experience on this or even never heard about it. It’s common that professors in colleges ignore this section.So, now if you need to transfer a signal from a slower clock domain to a faster one, what would you do? Assuming that you have as much time as you need on the receiver side to catch the signal which wold not changed frequently. 


Using back-to-back double registers.

Double Registers Synchronizer.png

Due to metastability of flip-flip (register), the first output O1 could be metastable due to its source from a slower clock. The second register is needed to settle the output O1. The O2 then will be stable.

If this is an FPGA Engineer Interview, the follow up question could be: How to constrain the synchronizer you make in Xilinx Vivado or Intel Quartus?

1. The receiver side FFs shall be put close to each other. Vivado and Quartus will both constrain back to back FFs closely in an automated way. If you are using Ultrascale series FPGA, you can use the provided Metastability hardened FF which can be applied as (*async_reg=”true”*). For Xilinx FPGA, we usually will also apply the set_max_delay between the receiver and transmitter clock domains:

set_max_delay -datapath_only -from [get_clocks TX_CLOCK] -to [get_clock RX_CLOCK] [expr min([join[get_property PERIOD [get_clocks “TX_CLOCK RX_CLOCK”]],])]

The interviewer would understand not everybody has tackled all these aspects of FPGA design flow, it’s less important than the synchronized design part.


  1. Passing a single-bit from slow clock to fast clock, with 2FF synchronizers might still possibly let receiver latch the same data multiple times.

    I think even with single bit, it’s right to use a valid ready interface and handshake protocol, in this slow to fast environment. Please let me know if my argument sounds reasonable.

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