The CPU runs programs in virtual address space, and the virtual address needs to translate to physical address before accessing system memory. Virtual memory is an often-asked-question in hardware interviews, and it reflects the interviewee’s overall understanding towards modern computer system.
Benefits of Virtual Memory
Virtual memory frees the applications from having to manage and allocate shared memory space. Instead, programs can operate in continuous virtual memory space while the actual physical memory space can be discontiguous. The physical memory management relies on operating system.
With virtual memory, programs are able to conceptually use more memory than might be physically available. For example, even though the physical memory is only 4GB, virtual address width can have more than 32 bits. The storage space can be extended using hard drive disk.
Virtual memory also increases the security due to memory isolation. During address translation, the accessibility is checked as well. If the program attempts to write to a memory address that is read only, the write access will be blocked, and an error will be signaled.
How does A Virtual Address Get Translated?
Virtual addresses are translated in granularity of page. Operating system will maintain a data structure called page table in memory, keeping track of the mapping from virtual page to physical page. The page table is indexed by virtual page number. An example of page table is shown below. Note the page offset is unchanged during virtual to physical address translation.
In addition, page table will store the accessibility and security information of the page table, which will be checked against during page translation.
TLB: Reducing Page Translation Cost
Since page table resides in main memory, each memory access involves two memory accesses. It will first do a page table walk and then perform the actual memory access, which can be quite expensive. This cost can be reduced by adding a cache to page table, or Translation Lookaside Buffers, or TLB. A 128-entry TLB example is shown below.
To perform a page translation, TLB will be looked up first. If the page is not in TLB, then page table is involved.
Unlike regular cache, there will be little or no spatial locality from page to page, thus TLBs are usually fully associative.
How to Handle a TLB Miss
It is possible that a page to translate does not reside in TLB. Usually there are 2 approaches to resolve a TLB miss:
- Software method. A TLB miss can cause an interrupt, and operating system will get involved to check the page table and update TLB. MIPS and Alpha use this method.
- Hardware method. A specially hardware called Memory Management Unit or MMU is involved to perform page table walk in main memory and update TLB. X86, SPARC and PowerPC use this method.
How to Handle a Page Fault
A page fault can happen when the page does not reside either in main memory, or in TLB. If a page fault happens, the page table entry has to be first brought into main memory by IO read from disk.
One key thing to remember, regardless how TLB miss is handled, page fault is always handled by operating system.