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`timescale 1ns / 1ps module sequence_detector( input clk, reset, din, output reg dout); localparam s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101; reg [2:0] state = 3'b000; always @ (posedge clk or posedge reset) begin if (reset) begin state <= s0; dout <= 1'b0; end else begin case (state) s0: begin dout <= 1'b0; if (!din) state <= s1; end s1: if (din) state <= s2; s2: if (!din) state <= s3; else state <= s0; s3: if (din) state <= s4; else state <= s0; s4: begin dout <= 1'b0; if (!din) state <= s5; else state <= s0; end s5: begin dout <= 1'b1; if (din) state <= s4; else state <= s1; end endcase end end endmodule |
Shouldn’t the S5 transition to S1 when the input is 0?
Correct! S5 -> S1
Thanks! Just corrected.