This is probably one of most frequently asked Digital/FPGA design interview questions. As we know, FIFO is usually used to buffer/queue data in a system block. So, as a design engineer, we need to decide what’s the minimal depth of the FIFO for the certain case.

The size of FIFO needs to be assigned big enough the volume of data needed to buffer. This also depends on how fast the data is written into and how fast the data is read out.

Thus, in the worse case, the write operation max data rate and the min read data rate shall be considered. Data rate = data volume * clock rate. Writing and reading sides are consider as source and sink. There might be some IdleCycles on the read side according to the ability to swallow from the next block.

So, we first need to figure out the number of data in a burst B.

 

The Buffer/FIFO Depth =

FIFO_size

For example, how do we design the synchronized FIFO depth/size given the following requirements:

  • Design a synchronized FIFO
  • Write frequency (Fwrite): 100Mhz
  • Read frequency (Fread): 40Mhz
  • Write Data Burst (B): 80 words
  • Read idle cycle: case A – 1 cycle, case B – 10 cycles

In case A: the minimal FIFO depth/size = 80 – (80*40)/(100*1) = 48 words

In case B: the minimal FIFO depth/size = 80 – (80*40)/(100*10) = 76.8 ~ 77 words

 

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