If you’re familiar with SRAM structure, for the same amount storage, dual-port SRAM takes more area than single-port SRAM, since each dual-port SRAM row needs 2 word lines. If we were to use single-port SRAM as FIFO memory storage, the area can be further reduced.

In one cycle, we can only have one read access or one write access to the single-port SRAM. But FIFO should be able to handle both read and write in the same cycle. This means we will need 2 banks of SRAM to sustain the bandwidth, and each bank has half of the required storage.

If there’s a bank conflict, i.e., read and write happen in the same bank, we can prioritize read over write, and write will be delayed to next cycle. The read and write accesses to 2 banks are interleaved, thus each bank can only be read or written every other cycle, and the delayed write is guaranteed to complete.

Same as dual-port SRAM, read latency is 1 cycle, so we will need data “prefetch” buffer to hide this latency.

The diagram below shows a possible implementation, which consists of identical 2 sets of logic. Each set of the logic is very similar to what we have seen in dual-port SRAM based FIFO, and we use read or write pointer LSBs to choose which set of the logic is active.

[T]Single-Port SRAM Based Sync FIFO


1 Comment

  1. I wish to know more details about this implementation

    Can you please explain how does read/write latency get affected for FIFO with single port SRAM? Does conditions for empty and full change?

    In this implementation, I suspect both read and write clock is assumed to be same, is that right ?

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.