Designing a power-of-2-entry async FIFO is straightforward, but how about designing an async FIFO with non-power-of-2 but even number of entries, for example, 6?

The only difficult part is non power of 2 number gray encoding. For power of 2 number is pretty straightforward. Let’s take 8 for example, the gray code can be:

000 -> 001 -> 011 -> 010 -> 110 -> 111 -> 101 -> 100

Notice that it’s mirror symmetric. To get gray encoding for 6, we can take the middle 2 encoding out of the sequence:

000 -> 001 -> 011 -> 111 -> 101 -> 100

It still satisfies gray encoding. Done!

How will you compute full and empty in this case?

It’s essentially the same as power-of-2 case. After syncing the pointer to another clock domain, do a gray-to-binary decoding, then compare the binary encoded pointer values.