When clock start rising, the outputs might start to change after the clock-to-q contamination delay, known as tccq and shall absolutely settle down to the stable value within the clock-to-q propagation delay, tpcq. They represent the shortest and longest delays through the circuit. In order for a circuit to sample its input correctly, the inputs must be stabilized at least some setup time, tsetup, before the rising edge of the clock and shall remain stable for at least hold time, thold.

The definition of setup time and hold time is often asked in hardware interviews. We recommend readers to memorize the definition. In next post, we will cover the setup time and hold time constraints.


  1. Set up and hold time is requirement for the receiver circuit to latch data bits correctly. On system design (board level), a driver has two interfaces, data and clock and sends them to the receiver circuit. A good design ensures enough margin in order to meet the setup and hold time of the receiver. Generally speaking, on the system level (PCB level design), clock jittery (intrinsic to driver circuit) and trace skew affects received signal’s integrity. Hence during layout phase of the hardware design, a tight skew control (trace length difference) between clock and data is enforced in the eCAD layout constraint manager forcing the PCB layout engineer to guarantee the data to clock skew below a safe margin. Once the PCB is fabricated and components are mounted, timing analysis using eye diagram measured at the receiver side is performed to for final signal integrity validation of the high speed communication interface.

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