In previous post, we discussed setup time and hold time definitions. We will cover the basics of STA: setup time and hold time constraints.
These constraints dictate the max and min delays of a computational logic between flip-flops. If any of the constraint is not met, we call it as timing violation. Timing violations lead to metastability.
Setup Time Constraint
Tc ≥ tpcq + tpd + tsetup
- Tc: clock period
- t_pcq: clock-to-q propagation delay,
- t_pd: propagation delay of whole circuit
- t_setup: setup time
Thus, the max propagation delay of the whole circuit, which designer can control, should be constraint as setup time constraint:
tpd ≤ Tc – (tpcq + tsetup)
Hold Time Constraint
tccq + tcd ≥ thold
- t_ccq: clock-to-q contamination delay
- t_cd: contamination delay of the whole circuit
- t_hold: hold time
Thus, the max propagation delay of the whole circuit, which designer can control, should be constraint as hold time constraint:
tcd ≥ thold – tccq
Taking Clock Skew Into Account
In real silicon, the absolute timestamps that clock rising edges arrive at launch flop and capture flop will be different, introducing clock skews. In a more accurate timing modeling, clock skew has to be taken into account. Clock skews can be positive when clock source is closer to launch flop, and both “data” and “clock” travel in the same direction. See the diagram below:
Obviously, positive clock skew helps setup timing closure, but hurts hold timing closure.
Clock skew can be negative. This happens when clock source is closer to capture flop, and “data” travels the opposite direction of “clock”. See the diagram below:
Obviously, negative clock skew helps hold timing closure, but hurts setup timing closure.
Now, the revised setup time and hold time constraints are shown below:
Tc + δ ≥ tpcq + tpd + tsetup
tccq + tcd ≥ thold + δ
The setup time and hold time constraints constitute the basics of STA, and these constraints should be kept in mind at all times. In next post, we will apply what we learnt in this post to practice, and explain what is the benefit of using half-cycle-path.