**Static Power**

Static power is proportional to circuit leakage current and supply voltage Vdd. Thus we have following ways to reduce static power:

- Dynamic Vth scaling by adjusting substrate bias
- Use multi-Vth devices in design
- Use high-Vth device whenever possible
- Dynamic supply voltage scaling
- Use multi-Vdd in design
- Shut off the power in standby mode

**Dynamic Power**

Assuming the signal toggles every cycle, then dynamic power can be measured by the formula below:

P = 0.5 * CL * Vdd * Vswing * f = 0.5 * CL * Vdd * (Vmax – Vmin) * f

Thus, to reduce the dynamic power, we can:

- Reduce voltage swing
- Use dynamic supply voltage scaling
- Use multi-Vdd in design
- Shut off the power in standby mode
- Reduce clock frequency
- Use dynamic frequency scaling
- Use multi clock in design
- Gate off the clock if the logic is inactive
- Reduce switching activity by reducing glitches
- Optimize logic and architecture, to reduce the load capacitance

**Short-circuit Dissipation Power**

To reduce short-circuit dissipation power, we have following ways in our toolkit:

- Reduce Vdd / switching activity / clock frequency, which is similar to dynamic power reduction
- Matching the rise / fall times of input and output signals across the chip. Although this is not the optimal solution for a particular gate on its own, we can keep the overall short-circuit current within bounds at the chip level
- If the supply is lowered to be below the sum of the thresholds of the transistors, Vdd < (VTn + |VTp|), the short-circuit currents can be eliminated because both devices will not be on at the same time for any value of input voltage

## 2 Comments