## Static Power

Static power is proportional to circuit leakage current and supply voltage Vdd. Thus we have following ways to reduce static power:

1. Dynamic Vth scaling by adjusting substrate bias
2. Use multi-Vth devices in design
3. Use high-Vth device whenever possible
4. Dynamic supply voltage scaling
5. Use multi-Vdd in design
6. Shut off the power in standby mode

## Dynamic Power

Assuming the signal toggles every cycle, then dynamic power can be measured by the formula below:

P = 0.5 * CL * Vdd * Vswing * f = 0.5 * CL * Vdd * (Vmax – Vmin) * f

Thus, to reduce the dynamic power, we can:

1. Reduce voltage swing
2. Use dynamic supply voltage scaling
3. Use multi-Vdd in design
4. Shut off the power in standby mode
5. Reduce clock frequency
6. Use dynamic frequency scaling
7. Use multi clock in design
8. Gate off the clock if the logic is inactive
9. Reduce switching activity by reducing glitches
10. Optimize logic and architecture, to reduce the load capacitance

## Short-circuit Dissipation Power

To reduce short-circuit dissipation power, we have following ways in our toolkit:

1. Reduce Vdd / switching activity / clock frequency, which is similar to dynamic power reduction
2. Matching the rise / fall times of input and output signals across the chip. Although this is not the optimal solution for a particular gate on its own, we can keep the overall short-circuit current within bounds at the chip level
3. If the supply is lowered to be below the sum of the thresholds of the transistors, Vdd < (VTn + |VTp|), the short-circuit currents can be eliminated because both devices will not be on at the same time for any value of input voltage